1. Field of the Invention
The invention relates generally to integrated circuits having repeated logic and interconnect structures provided therein. The invention relates more specifically to physical layouts for field programmable gate arrays (FPGA's).
2. Description of Related Art
As the density of digital logic circuitry within integrated circuits (IC's) increases, and as the signal-processing speed of such logic also increases, the ability of interconnect to route all signals in timely fashion between spaced-apart logic sections becomes more important to proper operation of the integrated circuit.
Physical layout within each logic section of an IC device may play a critical role in defining the signal-processing speed of the section. Device performance may also be affected by the physical separation between critical logic sections. Device performance may be further affected by the interplay between interconnect layout and logic layout.
More specifically, when it comes to the field of programmable logic arrays, artisans have begun to recognize that conductors of different lengths and orientations should be provided for servicing different kinds of signals. By way of example, a first class of relatively long, low resistance conductors may be provided for broadcasting common control signals (e.g., clock, clock enable, etc.) over relatively large distances of the IC device with minimal skew. Such special conductors are sometimes referred to as low-skew longlines. Artisans have also begun to realize that significantly shorter wire segments should be dedicated for transmitting logic input and logic output signals between immediately adjacent logic sections. These dedicated conductors are sometimes referred to as direct-connect lines.
At the same time, artisans wish to provide field programmable logic arrays with general-purpose conductors and general-purpose routing switches for carrying out general-purpose, programmable routing of signals.
This evolution toward using both general purpose and special purpose conductors within the interconnect portion of logic arrays needs to mesh with the concurrent evolution of logic circuits. The logic circuitry of logic array IC's is consistently evolving towards faster signal processing speeds and greater per area densities of logic functionalities. This confluence of developments has created a need for a physical layout of both interconnect and logic circuitry where such a layout efficiently accommodates design specifications for timing and processing of broadcast control signals, of high-speed local signals, and also of randomly-routed, general purpose signals.